# Blocking Assignment Verilog

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Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.

A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed Nonblocking assignment " agreed with research_vlsi.

In Below Example, a and b is initialized with value 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b.

After assignment value of a = 15 anmodule blocking_assignment; //variables declaration int a,b; initial begin \$display("-----------------------------------------------------------------"); //initializing a and b a = 10; b = 15; //displaying initial value of a and b \$display("\t Before Assignment :: Value of a is ",a); \$display("\t Before Assignment :: Value of b is ",b); a = b; b = 20; \$display("\t After Assignment :: Value of a is ",a); \$display("\t After Assignment :: Value of b is ",b); \$display("-----------------------------------------------------------------"); end ----------------------------------------------------------------- Before Assignment :: Value of a is 10 Before Assignment :: Value of b is 15 After Assignment :: Value of a is 15 After Assignment :: Value of b is 20 ----------------------------------------------------------------- In Below Example, a and b are initialized with value 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b.

Since, the value of ‘z’ is equal to ‘x’, therefore line 11 will be equivalent to ‘z = x y’; due to this reason, the design is generated as ‘and’ gate with inputs ‘x’ and ‘y’ as shown in In non-blocking assignment, updated values inside the block are not used for assignment.} In line 10, value of input port ‘x’ is assigned to the ‘z’.

Since updated value inside the block are not used in non-blocking assignment, therefore in line 11, ‘z = z & y;’, the old value of ‘z’ will be used for assignments (instead of z=x); hence a feedback path is used in .Then the right-hand side of the second nonblocking assignment statement is evaluated is also cached without changing b.Execution continues until it returns to the event statement, once there the execution of the process blocks until the next positive edge of the clk.In this case, the expression on the right hand side is evaluated and the value is held for 10 units of time.During this time, the execution of the code is blocked in the middle of the assignment statement.The best way of designing is to make small units using ‘continuous assignment statements’ and ‘procedural assignment statements’, and then use the structural modeling style to create the large system.In line 10, value of input port ‘x’ is assigned to output ‘z’.In that chapter, ‘if’ keyword was used in the ‘always’ statement block.This chapter presents some more such keywords which can be used in procedural assignments.Also, ‘x’ has no effect on the design as it is updating ‘z’ inside the block, which will not be used by non-blocking assignment; hence ‘x’ is not connected (i.e.connected to ground) in the design as shown in Note The block and non-blocking assignments can not be used together for a signal.

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